Regviz

Cypress Semiconductor /psoc63 /SMIF0 /INTR_SET

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as INTR_SET

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Cypress Semiconductor/psoc63/SMIF0/INTR_SET#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TR_TX_REQ)TR_TX_REQ 0 (TR_RX_REQ)TR_RX_REQ 0 (XIP_ALIGNMENT_ERROR)XIP_ALIGNMENT_ERROR 0 (TX_CMD_FIFO_OVERFLOW)TX_CMD_FIFO_OVERFLOW 0 (TX_DATA_FIFO_OVERFLOW)TX_DATA_FIFO_OVERFLOW 0 (RX_DATA_FIFO_UNDERFLOW)RX_DATA_FIFO_UNDERFLOW

Description

Interrupt set register

Fields

TR_TX_REQ

Write with ‘1’ to set corresponding bit in interrupt request register.
TR_RX_REQ

Write with ‘1’ to set corresponding bit in interrupt request register.
XIP_ALIGNMENT_ERROR

Write with ‘1’ to set corresponding bit in interrupt request register.
TX_CMD_FIFO_OVERFLOW

Write with ‘1’ to set corresponding bit in interrupt request register.
TX_DATA_FIFO_OVERFLOW

Write with ‘1’ to set corresponding bit in interrupt request register.
RX_DATA_FIFO_UNDERFLOW

Write with ‘1’ to set corresponding bit in interrupt request register.

Links

()

Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data